1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to the generation of layouts for integrated circuits including the layouts for the power supply within those integrated circuits.
2. Description of the Prior Art
It is known to provide mechanisms, such as appropriately programmed general purpose computers, that generate layouts for integrated circuits using libraries of standard cell designs and data defining the functionality and/or the circuits to be provided. This process is termed synthesis. One stage in the synthesis process is placing the standard cells at appropriate positions within the integrated circuit so that they are relatively nearby the other standard cells with which they need to communicate. A routing step then generates the conductors to route signals between the standard circuit cells which have been placed. Metal layers, such as the first metal layer, are normally used for such signal routing. Placement and signal routing are facilitated when there is a high degree of flexibility in the routing which may be provided, i.e. routing hotspots may be reduced and signal paths may be shortened.
Another part of the generation of layouts for an integrated circuit is the provision of the power supply for the circuitry formed from the standard cells. The power supply is typically provided by running power rail conductors across the integrated circuit at a regular spacing and parallel to one another. The standard cells are then be linked to these power supply rails so as to draw electrical energy therefrom. One known technique is to use a second metal layer to provide power rail conductors running across the integrated circuit. Power connection conductors positioned at least partially overlaid by the power rail conductors and provided within a first metal layer are used to connect the power rail conductors to appropriate points within the standard cells using connection vias. Providing the power connection conductors in the first metal layer in combination with the power rail conductors of the second metal layer enables gaps to be provided between the power connection conductors within the first metal layer thereby allowing signal routing conductors within the first metal layer to pass beneath the power rail conductors and provide signal porosity via the first metal layer in a direction perpendicular to the power rail conductors. This ability to provide routing conductors running under the power rail conductors helps reduce routing hotspots and enables more efficient placement.
A problem with the above use of power connection conductors within the first metal layer to link power from the power rail conductors to the circuits of the standard cells is that the via connections between the power rail conductor and the power connection conductor are a potential source of manufacturing errors which can disadvantageously reduce the manufacturing yield. If the via connections between the power rail conductor within the second metal layer and the power connection conductor within the first metal layer are not properly formed, then the power supply to an associated standard cell will not operate correctly leading to a failure of the integrated circuit. As integrated circuits increase in complexity and have increased numbers of standard cells therein, there is an increased likelihood of an error occurring in the via connections between the power rail conductors and the power connection conductors resulting in a failed component.